Verilog-based Hardware Implementation of ASIC Interface Involving Quad AMBA AHB Masters

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2020
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System-on-Chip (SoC), ASIC commonly integrates processor and other blocks to implement a very complex application. The processor in an ASIC accesses its targets using an interface that provides protocol conversation for all the targets. While the computation performance of processors increases, data throughput becomes the bottleneck. Moreover, as processors and rest of the ASIC need to share data and control/status, inter processors/ASIC communications become a serious issue. While various system interconnects have been introduced, processor interface architecture remains conceptually the same. To address this issue, this research considers using multiple processors for simultaneous access to their targets. This research address to come up with a multi-processor interface with an arbitration system to managing multiprocessor access considering two categories of priority: fixed arbitration or round-robin arbitration. Finally, for better throughput, this research considers the option of a coalescing system for bulk data access. In addition to better novel functionalities, three design constraints of ASIC, speed, low power, and low area are in primary consideration to improve in this research work. This research is expected to achieve an efficient interface ASIC with an intelligent arbitration system. A smart coalescing technique and targets to be used as a separate ASIC which integrated with IP or a macroblock in any SoC. This particular type of multiple processors can be used in the area of networking like host bus adapters, Ethernet system, a network switch, including controllers in many digital devices and equipment.
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Electrical and Computer Engineering
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North South University
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